1. Field
The following description relates to a register file and computing device using the same.
2. Description of the Related Art
Reconfigurable architecture refers to architecture in which a hardware configuration of a computing device may be changed to optimally perform a task.
When a task is only processed in a hardware environment, it is difficult to efficiently process the task after the task's process is changed because of the fixed nature of hardware. In contrast, if a task is only processed in a software environment, the task can be processed by reconfiguring software to suit a process of the task, but processing speed of the task may be slower when processed in a software environment than when the task is processed in a hardware environment.
The reconfigurable architecture process tasks based on both hardware and software advantages. Recently, such reconfigurable architecture has drawn more attention from a digital signal processing field which executes the same task iteratively.
One of a variety of types of reconfigurable architecture is a coarse-grained array. The coarse-grained array includes a number of processing units. For the coarse-grained array, the number of processing units are adjusted to optimally perform a specific task.
In the coarse-grained array, a plurality of processing units are capable of processing different threads concurrently. For example, in the case of threads #0 and #1 which can be processed in parallel, processing unit #0 can process the thread #0 and processing unit #1 can process the thread #1. However, when the threads #0 and #1 refer to the same register, it is not possible to ensure effective multi-threading. In this case, when a programmer makes a code directly, or a compiler compiles a source code, threads need to be appropriately scheduled, which may cause overhead in a multi-thread system.